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Vikulin Vladimir

Male, 60 years, born on 14 January 1964

Considers offers
Contacts
 +7 (911) 286-93-24
Телефон подтвержден
v_vikulin@mail.ru — preferred means of communication
Method of contact
 LinkedIn vladimir.vikulin

Saint Petersburg, willing to relocate, prepared for business trips

team leader; head of department

Specializations:
  • Development team leader

Employment: full time, part time, project work

Work schedule: full day, remote working

Work experience 19 years

July 2016 — currently
7 years 11 months
MacroGroup

Russia, www.macrogroup.ru

Electronics, Tool Engineering, Household Appliances, Computers and Office Equipment... Show more

Xilinx FAE
- Expert in Xilinx FPGA, SoC and Developement tools - Exelent knowlige of Vivado, VivadoHLS, SDK, and other tools. - Tech support and developing tech solutions for customers - Leader of Xilinx products public tech seminars and webinars - Own Projects: release of G722.1 coder for Artix7 FPGA in VivadoHLS; videocontroller 1980x1020@120HZ with PIP function for Genesys2 dev board - Took part in Xilinx TSC 2017, Dublin, Ireland and XDF-2019, Haag, Netherlands
June 2014 — June 2016
2 years 1 month
UHBlab, ltd, dealer of Achronix, corp

Saint Petersburg, achronix.ru

Electronics, Tool Engineering, Household Appliances, Computers and Office Equipment... Show more

Chief engineer
Solving all issues concerning to usage of FPGA Achronix: instrumental tools; demodesigns, customer support and so on
October 2013 — May 2014
8 months
Kometeh, ltd

Saint Petersburg, kometeh.ru

Electronics, Tool Engineering, Household Appliances, Computers and Office Equipment... Show more

Head of the FPGA Developement Department
Along with the management and planning, keep on FPGA design activity
October 2011 — September 2013
2 years
Kometeh, ltd

Saint Petersburg, kometeh.ru

Electronics, Tool Engineering, Household Appliances, Computers and Office Equipment... Show more

LEAD hardware engineer
FPGA design: Verilog coding, verification and implementation for of Ethernet testers MAKS-EM10 and MAKS-EMB (10/100/1000 Mb Ethernet). Working with ALTERA's FPGA Cyclone III. Responsible for all of the FPGA design process of the company. HDL languages: Verilog, SystemVerilog, VHDL. Excellent experience in Modelsim. Good knowledge of Quartus-II design tools.
June 2008 — June 2011
3 years 1 month
"Lanit-Tercom", ltd

Saint Petersburg, lanit-tercom.com

Electronics, Tool Engineering, Household Appliances, Computers and Office Equipment... Show more

LEAD hardware engineer
HDL design for Xilinx Virtex-5, and Spartan-6 FPGA's in VHDL Designed a number of SOC on LEON-3 and PPC-440 CPU cores and a lot of functional IP's for Ethernet, telecommunication and video-processing purposes.
February 2006 — May 2008
2 years 4 months
“Deep Life Design Team”, Ltd

Saint Petersburg

Electronics, Tool Engineering, Household Appliances, Computers and Office Equipment... Show more

Electronic Engineer
HDL design and verification for Xilinx Virtex-4, and Spartan-3 FPGA's and QuickLogic's antifuse FPGA's in Verilog, including life-critical design.
March 2005 — January 2006
11 months
ACTEL.RU (exclusive representative of company ACTEL in Russia and Ukrain)

Saint Petersburg

Electronics, Tool Engineering, Household Appliances, Computers and Office Equipment... Show more

Field Application Engineer (FAE)
• Tech support of customers, including business trips to our customers companies • Tech seminars and trainings for our customers • Tech literature creating and translating (have articles, published in “Electronic components” magazine) • Marketing, Direct marketing • Direct Marketing, representing Actel's products and solutions in exhibitions

Key skills

You can change skill levels in the mobile app — the website will have this feature a little later on

fpga
SVN
Git
C/C++
Linux
Driving Licence B
Verilog HDL
VHDL
IAR
ARM
embedded systems
Customer Support

Driving experience

Own car

Driver's license category B, C

About me

HDL: Verilog/SystemVerilog, VHDL, HLS FPGA: Xilinx (Virtex US+ 4,5,6,7 series, Versal, XynqUS+, Zynq7000), Altera, Achronix, Microsemi(Actel), QuickLogic Excellent experience in verification/simulation process in Modelsim (Questasim) (ovm, uvm metodologies ...). Familiar with design tools: Vivado, VivadoHLS, ISE, Quartus-II, Achronix's ACE, Libero, Precision, Sinplify, FPGA Advantage IP cores: Ethernet cores, PCIe cores and many others. SoC design based on i186, Leon-3, PPC-440, ARM, STM32, MSP-430, MIPS, RISC-V and other CPU cores Programming languages: C/C++, TCL, PHP, perl and many others. IAR embedded workbench Operating systems: Windows and Linux. Project management: gitlab, TRAC. Code repository: svn, git Experienced tech writer Excellent communication skills Experienced tech supporter with deep understanding customer's problems

Recommendations

-
Avaliable under request (-) 

Higher education

1986
Leningrad Electrotehnical Institute (LETI)
AFDN, “Applied Math”, Engineer-Matematic

Languages

Russian — Native


English — C1 — Advanced


Professional development, courses

2019
XDF 2019, Haag, Netherlands
Xilinx, Conference for new products and developement tools of Xilinx including Versal and Vivado
2017
Xilinx Tehnical Sales Conference, Dublin, Ireland
Xilinx, Deep dive training for all aspects of applying Xilinx FPGAs, SoCs, tools and innovations
2005
ACTEL FAE and SALES Conference, Santa Clara, California, USA
ACTEL, -

Citizenship, travel time to work

Citizenship: Russia

Permission to work: Russia

Desired travel time to work: Doesn't matter